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IST Lunch Bunch
Tuesday November 2, 2010
12:00 PM
105 Annenberg
A (Hypothetical) Data to Discovery Engine
Mark Stalzer, Caltech – CACR
Description/Abstract:
Moore’s law works for semiconductor-based detectors and there is an increasing flood of data being generated in astronomy, high energy physics, biology, and other sciences. Computation is essential for both (1) making predictions from theory and (2) the analysis of data from experiments. Is there a way to architecturally balance both needs in a high performance computing (HPC) system?
HPC systems are typically constructed from easily available parts, just organized differently and scaled to process extreme workloads. The most power efficient petascale machine as of 2010 is Roadrunner at the Los Alamos National Laboratory. Another interesting machine is the Apple iPad which uses very low power System on a Chip/Package on Package technologies. This talk explores the question of “what happens when you cross Roadrunner with iPads”? The result is a high level of integration between computation and storage on a single server blade, called a Flashblade, with 100x-1,000x performance improvements for some data-centric applications. The Flashblade architecture, expected performance, programming, and scaling with advancing technology are discussed.
(See publication page for PDF link)
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An award of $994,408 from the National Science Foundation was made to the project entitled “Development of a Research Infrastructure for the Multithreaded Computing Community Using the Cray XMT Platform.” The subcontract for Caltech/CACR (PI Ed Upchurch) will fund the porting of significant science applications to an XMT system. CACR will assess the XMT’s performance and compare it with the performance on other parallel architectures at CACR.
With the advent of MPI and Linux clusters, message-passing architectures are today the dominant approach for parallel computing systems, and the high-end computing community has developed a strong infrastructure to support this. With the trend towards multicore processors, however, the situation is changing. The major processor developers all envision placing tens to hundreds of cores on a single die, each running multiple threads. To take advantage of this, the CS community will need focus on how to develop efficient multithreaded programs in shared memory. The goal of the project is to bring a diverse group of researchers with extensive experience with shared-memory multithreading together as a community, and to jointly develop a shared infrastructure needed to broaden its impact for developing software to run on the next generation of computer hardware.
The first objective of the program is to acquire computer hardware as a shared community resource capable of efficiently running, in experimental and production modes, complex programs with thousands of threads in shared memory. The Cray XMT system, scheduled for delivery in the first half of 2008, is an ideal platform for this.
The second objective of the program is assembling a software infrastructure for developing and measuring the performance of programs running on this hardware. This will include algorithms, data sets, libraries, languages, tools, and simulators to evaluate architectural enhancements for future hardware.
The third objective of the project building stronger ties between the people themselves, creating ways for researchers at the partner institutions to collaborate and communicate their findings to the broader community.
The academic partners on the team are the University of Notre Dame, Georgia Institute of Technology, University of California, Berkeley, University of California, Santa Barbara, University of Delaware, and the California Institute of Technology. The team will also collaborate with Sandia National Laboratories, who has agreed to host the Cray XMT system and will provide supplementary funding.
For further information on the Caltech subcontract, contact Ed Upchurch
