Caltech Center for Advanced Computing Research » Posts for tag 'exascale computing'

CACR Seminar: “The Technical Challenges of Exascale Computing”

Professor Peter Kogge
University of Notre Dame

March 12, 2010
2PM
147 Noyes

Abstract

DARPA recently funded a 2 year study of the technical challenges of trying to go from today’s petascale computing to exascale – 1000X – in roughly half the time it took to get from terascale to petascale. This talk will summarize this study, with a particular focus on the most far-reaching of the challenges, namely energy. This will be expanded on by an overview of a recent study of energy consumption within the Linpack algorithm which indicates strongly that we have probably crossed a threshold where the real energy and power problems of the future are in the memory and interconnect – not the processing logic.

Bio

Dr. Peter Kogge currently holds the Ted McCourtney Chair of Computer Engineering at the University of Notre Dame, with research interests in highly scalable computer architectures and nano-technologies. Prior to that he was an IBM Fellow with IBM’s Federal System where among other projects he oversaw the development of arguably the world’s first multi-core chip in 1993 – on a DRAM process. He is the author of 2 books, including the first on the now ubiquitous technique of pipelining, and holds over 30 patents. Applications of his PhD research led to what is now called the Kogge-Stone adder, the fastest known adder constructed out of fixed fanout gates. He was also the chairman of the DARPA working group that developed the Exascale report.