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	<title>CACR Research Publications &#187; high-performance computing</title>
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		<title>A (Hypothetical) Data to Discovery Engine (v2)</title>
		<link>http://www.cacr.caltech.edu/pubs/?p=496</link>
		<comments>http://www.cacr.caltech.edu/pubs/?p=496#comments</comments>
		<pubDate>Tue, 02 Nov 2010 16:37:19 +0000</pubDate>
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				<category><![CDATA[Uncategorized]]></category>
		<category><![CDATA[high-performance computing]]></category>

		<guid isPermaLink="false">http://www.cacr.caltech.edu/pubs/?p=496</guid>
		<description><![CDATA[Mark Stalzer, Caltech &#8211; CACR
Seminar given at &#8220;IST Lunch Bunch&#8221;
Tuesday November 2, 2010
12:00 PM
105 Annenberg
Abstract:
Moore&#8217;s law works for semiconductor-based detectors and there is an increasing flood of data being generated in astronomy, high energy physics, biology, and other sciences. Computation is essential for both (1) making predictions from theory and (2) the analysis of data [...]]]></description>
			<content:encoded><![CDATA[<p>Mark Stalzer, Caltech &#8211; CACR</p>
<p>Seminar given at &#8220;IST Lunch Bunch&#8221;<br />
Tuesday November 2, 2010<br />
12:00 PM<br />
105 Annenberg</p>
<p>Abstract:<br />
Moore&#8217;s law works for semiconductor-based detectors and there is an increasing flood of data being generated in astronomy, high energy physics, biology, and other sciences. Computation is essential for both (1) making predictions from theory and (2) the analysis of data from experiments. Is there a way to architecturally balance both needs in a high performance computing (HPC) system?</p>
<p>HPC systems are typically constructed from easily available parts, just organized differently and scaled to process extreme workloads. The most power efficient petascale machine as of 2010 is Roadrunner at the Los Alamos National Laboratory. Another interesting machine is the Apple iPad which uses very low power System on a Chip/Package on Package technologies. This talk explores the question of “what happens when you cross Roadrunner with iPads”? The result is a high level of integration between computation and storage on a single server blade, called a Flashblade, with 100x-1,000x performance improvements for some data-centric applications. The Flashblade architecture, expected performance, programming, and scaling with advancing technology are discussed.</p>
<p>(<a href="http://www.cacr.caltech.edu/pubs/?attachment_id=497">PDF</a>)</p>
]]></content:encoded>
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		<item>
		<title>A (Hypothetical) Data to Discovery Engine</title>
		<link>http://www.cacr.caltech.edu/pubs/?p=478</link>
		<comments>http://www.cacr.caltech.edu/pubs/?p=478#comments</comments>
		<pubDate>Mon, 21 Jun 2010 17:16:12 +0000</pubDate>
		<dc:creator>cacrweb</dc:creator>
				<category><![CDATA[Uncategorized]]></category>
		<category><![CDATA[high-performance computing]]></category>

		<guid isPermaLink="false">http://www.cacr.caltech.edu/pubs/?p=478</guid>
		<description><![CDATA[AstroInformatics 2010
Caltech, June 16-19, 2010
Mark Stalzer
High performance computing systems are typically constructed from easily available parts, just organized differently and scaled to process extreme workloads. The most power efficient petascale machine as of 2010 is Roadrunner at the Los Alamos National Laboratory. Another interesting machine is the Apple iPad which uses very low power System [...]]]></description>
			<content:encoded><![CDATA[<p><a href="http://www.astroinformatics2010.org/">AstroInformatics 2010</a><br />
Caltech, June 16-19, 2010</p>
<p><strong>Mark Stalzer</strong></p>
<p>High performance computing systems are typically constructed from easily available parts, just organized differently and scaled to process extreme workloads. The most power efficient petascale machine as of 2010 is Roadrunner at the Los Alamos National Laboratory. Another interesting machine is the Apple iPad which uses very low power System on a Chip/Package on Package technologies. This talk explores the question of &#8220;what happens when you cross Roadrunner with iPads&#8221;?</p>
<p>(<a href="http://www.cacr.caltech.edu/pubs/?attachment_id=494">PDF</a>)</p>
]]></content:encoded>
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		<item>
		<title>Applications Architecture Power Puzzle &#8211; SC09 Panel</title>
		<link>http://www.cacr.caltech.edu/pubs/?p=451</link>
		<comments>http://www.cacr.caltech.edu/pubs/?p=451#comments</comments>
		<pubDate>Thu, 10 Dec 2009 22:42:58 +0000</pubDate>
		<dc:creator>cacrweb</dc:creator>
				<category><![CDATA[Uncategorized]]></category>
		<category><![CDATA[architecture]]></category>
		<category><![CDATA[high-performance computing]]></category>
		<category><![CDATA[SC09]]></category>

		<guid isPermaLink="false">http://www.cacr.caltech.edu/pubs/?p=451</guid>
		<description><![CDATA[Click names for presentation PDF.
Moderator:

Mark Stalzer, CACR

Panelists:

Thomas Sterling, Louisiana State University
Allan Snavely, San Diego Supercomputer Center
Stephen Poole, Oak Ridge National Laboratory
William Camp, Intel Corporation

Abstract:
Over the next few years there are two boundary conditions that should constrain computer systems architecture: commodity components and applications performance. Yet, these two seem strangely disconnected. Perhaps we need some human [...]]]></description>
			<content:encoded><![CDATA[<p>Click names for presentation PDF.</p>
<p><strong>Moderator:</strong></p>
<ul>
<li><a href="http://www.cacr.caltech.edu/pubs_uploads/ArchPanelSC09/Stalzer.pdf"><strong>Mark Stalzer</strong></a>, CACR</li>
</ul>
<p><strong>Panelists:</strong></p>
<ul>
<li><a href="http://www.cacr.caltech.edu/pubs_uploads/ArchPanelSC09/Sterling.pdf">Thomas Sterling</a>, Louisiana State University</li>
<li><a href="http://www.cacr.caltech.edu/pubs_uploads/ArchPanelSC09/Snavely.pdf">Allan Snavely</a>, San Diego Supercomputer Center</li>
<li>Stephen Poole, Oak Ridge National Laboratory</li>
<li>William Camp, Intel Corporation</li>
</ul>
<p><strong>Abstract:</strong><br />
Over the next few years there are two boundary conditions that should constrain computer systems architecture: commodity components and applications performance. Yet, these two seem strangely disconnected. Perhaps we need some human optimization, as opposed to repeated use of Moore’s Law. Our panelists have been given a set of standard components that are on announced vendor roadmaps. They also each get to make one mystery component of no more complexity than a commercially available FPGA. The applications are HPL for linear algebra, Map-Reduce for databases, and a sequence matching algorithm for biology. The panelists have 10 minutes to disclose their systems architecture and mystery component, and estimate performance for the three applications at 1MW of power.</p>
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		<item>
		<title>Whole-volume integrated gyrokinetic simulation of plasma turbulence in realistic diverted-tokamak geometry</title>
		<link>http://www.cacr.caltech.edu/pubs/?p=423</link>
		<comments>http://www.cacr.caltech.edu/pubs/?p=423#comments</comments>
		<pubDate>Fri, 17 Jul 2009 22:41:58 +0000</pubDate>
		<dc:creator>cacrweb</dc:creator>
				<category><![CDATA[Uncategorized]]></category>
		<category><![CDATA[CPES]]></category>
		<category><![CDATA[gyrokinetic plasma simulation]]></category>
		<category><![CDATA[high-performance computing]]></category>
		<category><![CDATA[multiscale modeling]]></category>

		<guid isPermaLink="false">http://www.cacr.caltech.edu/pubs/?p=423</guid>
		<description><![CDATA[SciDAC 2009, Journal of Physics: Conference Series. J Phys: Conf Ser 180 (2009) 012057.
C S Chang, S Ku, P Diamond, M Adams, R Barreto, Y Chen, J Cummings, E D&#8217;Azevedo, G Dif-Pradalier, S Ethier, L Greengard, T S Hahm, F Hinton, D Keyes, S Klasky, Z Lin, J Lofstead, G Park, S Parker, N Podhorszki, [...]]]></description>
			<content:encoded><![CDATA[<p>SciDAC 2009, Journal of Physics: Conference Series. J Phys: Conf Ser 180 (2009) 012057.</p>
<p>C S Chang, S Ku, P Diamond, M Adams, R Barreto, Y Chen, <strong>J Cummings</strong>, E D&#8217;Azevedo, G Dif-Pradalier, S Ethier, L Greengard, T S Hahm, F Hinton, D Keyes, S Klasky, Z Lin, J Lofstead, G Park, S Parker, N Podhorszki, K Schwan, A Shoshani, D Silver, M Wolf, P Worley, H Weitzner, E Yoon and D Zorin</p>
]]></content:encoded>
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		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Scaling to 150K cores: recent algorithm and performance engineering developments enabling XGC1 to run at scale</title>
		<link>http://www.cacr.caltech.edu/pubs/?p=421</link>
		<comments>http://www.cacr.caltech.edu/pubs/?p=421#comments</comments>
		<pubDate>Fri, 17 Jul 2009 22:40:51 +0000</pubDate>
		<dc:creator>cacrweb</dc:creator>
				<category><![CDATA[Uncategorized]]></category>
		<category><![CDATA[CPES]]></category>
		<category><![CDATA[high-performance computing]]></category>
		<category><![CDATA[particle-in-cell methods]]></category>
		<category><![CDATA[plasma simulation]]></category>

		<guid isPermaLink="false">http://www.cacr.caltech.edu/pubs/?p=421</guid>
		<description><![CDATA[SciDAC 2009, Journal of Physics: Conference Series. J Phys: Conf Ser 180 (2009) 012036.
M Adams, S Ku, P Worley, E D&#8217;Azevedo, J Cummings and C S Chang
]]></description>
			<content:encoded><![CDATA[<p>SciDAC 2009, Journal of Physics: Conference Series. J Phys: Conf Ser 180 (2009) 012036.</p>
<p>M Adams, S Ku, P Worley, E D&#8217;Azevedo, <strong>J Cummings</strong> and C S Chang</p>
]]></content:encoded>
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		</item>
		<item>
		<title>Porting Some Key Caltech &amp; JPL Applications to a PS3 Cluster &#8211; A Wild Ride</title>
		<link>http://www.cacr.caltech.edu/pubs/?p=344</link>
		<comments>http://www.cacr.caltech.edu/pubs/?p=344#comments</comments>
		<pubDate>Tue, 30 Sep 2008 17:26:48 +0000</pubDate>
		<dc:creator>cacrweb</dc:creator>
				<category><![CDATA[Uncategorized]]></category>
		<category><![CDATA[cluster]]></category>
		<category><![CDATA[high-performance computing]]></category>
		<category><![CDATA[PS3]]></category>

		<guid isPermaLink="false">http://www.cacr.caltech.edu/pubs/?p=344</guid>
		<description><![CDATA[High Performance Embedded Computing Workshop,/ Lexington, MA, September 2008.
Paul Springer, Ed Upchurch, Mark Stalzer, Sean Mauch, John McCorquodale, Jan Lindheim, and Michael Burl
(PDF)
]]></description>
			<content:encoded><![CDATA[<p>High Performance Embedded Computing Workshop,/ Lexington, MA, September 2008.</p>
<p>Paul Springer, <strong>Ed Upchurch</strong>, <strong>Mark Stalzer</strong>, <strong>Sean Mauch</strong>, <strong>John McCorquodale</strong>, <strong>Jan Lindheim</strong>, and Michael Burl</p>
<p>(<a href="http://www.ll.mit.edu/HPEC/agendas/proc08/agenda.html">PDF</a>)</p>
]]></content:encoded>
			<wfw:commentRss>http://www.cacr.caltech.edu/pubs/?feed=rss2&amp;p=344</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>The &#8220;MIND&#8221; Scalable PIM Architecture</title>
		<link>http://www.cacr.caltech.edu/pubs/?p=188</link>
		<comments>http://www.cacr.caltech.edu/pubs/?p=188#comments</comments>
		<pubDate>Mon, 20 Jun 2005 18:21:09 +0000</pubDate>
		<dc:creator>cacrweb</dc:creator>
				<category><![CDATA[Uncategorized]]></category>
		<category><![CDATA[architecture]]></category>
		<category><![CDATA[high-performance computing]]></category>
		<category><![CDATA[MIND]]></category>
		<category><![CDATA[PIM]]></category>

		<guid isPermaLink="false">http://www.cacr.caltech.edu/pubs/?p=188</guid>
		<description><![CDATA[In: Advanced Research Workshop on High Performance Computing Technology and Applications, 31 May-3 June, 2004, Cetraro, Italy.  [CaltechCACR:2005.102] 
Thomas Sterling and Maciej Brodowicz
(PDF )
]]></description>
			<content:encoded><![CDATA[<p><span class="citation">In: <span class="field_event_title">Advanced Research Workshop on High Performance Computing Technology and Applications</span>, <span class="field_event_dates">31 May-3 June, 2004</span>, <span class="field_event_location">Cetraro, Italy</span>.  [<span class="field_id_number">CaltechCACR:2005.102</span>] </span></p>
<p><span class="citation"><span class="field_creators"><strong><span class="person_name">Thomas Sterling</span></strong> and <strong><span class="person_name">Maciej Brodowicz</span></strong></span></span></p>
<p><span class="citation">(<a href="http://cacr.library.caltech.edu/105/"><em><span class="field_title">PDF</span></em></a> )</span></p>
]]></content:encoded>
			<wfw:commentRss>http://www.cacr.caltech.edu/pubs/?feed=rss2&amp;p=188</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Reusable and Extensible High Level Data Distributions</title>
		<link>http://www.cacr.caltech.edu/pubs/?p=174</link>
		<comments>http://www.cacr.caltech.edu/pubs/?p=174#comments</comments>
		<pubDate>Fri, 20 May 2005 17:27:43 +0000</pubDate>
		<dc:creator>cacrweb</dc:creator>
				<category><![CDATA[Uncategorized]]></category>
		<category><![CDATA[high-performance computing]]></category>
		<category><![CDATA[parallel processing]]></category>

		<guid isPermaLink="false">http://www.cacr.caltech.edu/pubs/?p=174</guid>
		<description><![CDATA[In: Workshop on Patterns in High Performance Computing, 4-6 May, 2005, University of Illinois at Urbana-Champaign. 
Roxana E. Diaconescu, Bradford Chamberlain and Hans P. Zima (2005)
(PDF)
]]></description>
			<content:encoded><![CDATA[<p><span class="citation">In: <span class="field_event_title">Workshop on Patterns in High Performance Computing</span>, <span class="field_event_dates">4-6 May, 2005</span>, <span class="field_event_location">University of Illinois at Urbana-Champaign</span>. </span></p>
<p><span class="citation"><span class="field_creators"><strong><span class="person_name">Roxana E. Diaconescu</span></strong>, <span class="person_name">Bradford Chamberlain</span> and <span class="person_name">Hans P. Zima</span></span> (<span class="field_date_effective">2005</span>)</span></p>
<p>(<a href="http://cacr.library.caltech.edu/107/">PDF</a>)</p>
]]></content:encoded>
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		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Continuum Computer Architecture for Nano-scale and Ultra-high Clock Rate Technologies</title>
		<link>http://www.cacr.caltech.edu/pubs/?p=178</link>
		<comments>http://www.cacr.caltech.edu/pubs/?p=178#comments</comments>
		<pubDate>Thu, 20 Jan 2005 17:33:50 +0000</pubDate>
		<dc:creator>cacrweb</dc:creator>
				<category><![CDATA[Uncategorized]]></category>
		<category><![CDATA[high-performance computing]]></category>

		<guid isPermaLink="false">http://www.cacr.caltech.edu/pubs/?p=178</guid>
		<description><![CDATA[In: International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, January 17-19, 2005, Oahu, Hawaii.  [CaltechCACR:2005.101] 
Thomas Sterling and Maciej Brodowicz
(PDF)
]]></description>
			<content:encoded><![CDATA[<p><span class="citation">In: <span class="field_event_title">International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems</span>, <span class="field_event_dates">January 17-19, 2005</span>, <span class="field_event_location">Oahu, Hawaii</span>.  [<span class="field_id_number">CaltechCACR:2005.101</span>] </span></p>
<p><span class="citation"><span class="field_creators"><strong><span class="person_name">Thomas Sterling</span></strong> and <strong><span class="person_name">Maciej Brodowicz</span></strong></span></span></p>
<p>(<a href="http://cacr.library.caltech.edu/104/">PDF</a>)</p>
]]></content:encoded>
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		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>21st Century Simulation: Exploiting High Performance Computing and Data Analysis</title>
		<link>http://www.cacr.caltech.edu/pubs/?p=352</link>
		<comments>http://www.cacr.caltech.edu/pubs/?p=352#comments</comments>
		<pubDate>Thu, 16 Dec 2004 17:45:25 +0000</pubDate>
		<dc:creator>cacrweb</dc:creator>
				<category><![CDATA[Uncategorized]]></category>
		<category><![CDATA[high-performance computing]]></category>

		<guid isPermaLink="false">http://www.cacr.caltech.edu/pubs/?p=352</guid>
		<description><![CDATA[ In: The Interservice/Industry Training, Simulation and Education Conference (I/ITSEC), 6-9 December, 2004, Orlando, FL. 
Dan M. Davis, Garth D. Baer and Thomas D. Gottschalk 
(PDF)

]]></description>
			<content:encoded><![CDATA[<p><span class="citation"><span class="field_creators"></span><a href="http://cacr.library.caltech.edu/94/"><em></em></a> In: <span class="field_event_title">The Interservice/Industry Training, Simulation and Education Conference (I/ITSEC)</span>, <span class="field_event_dates">6-9 December, 2004</span>, <span class="field_event_location">Orlando, FL</span>. </span></p>
<p><span class="citation"><span class="field_creators"><span class="person_name">Dan M. Davis</span>, <span class="person_name">Garth D. Baer</span> and <strong><span class="person_name">Thomas D. Gottschalk</span></strong></span> </span></p>
<p><span class="citation">(<a href="http://cacr.library.caltech.edu/94/">PDF</a>)<br />
</span></p>
]]></content:encoded>
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