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	<title>CACR Research Publications &#187; SC09</title>
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		<title>Applications Architecture Power Puzzle &#8211; SC09 Panel</title>
		<link>http://www.cacr.caltech.edu/pubs/?p=451</link>
		<comments>http://www.cacr.caltech.edu/pubs/?p=451#comments</comments>
		<pubDate>Thu, 10 Dec 2009 22:42:58 +0000</pubDate>
		<dc:creator>cacrweb</dc:creator>
				<category><![CDATA[Uncategorized]]></category>
		<category><![CDATA[architecture]]></category>
		<category><![CDATA[high-performance computing]]></category>
		<category><![CDATA[SC09]]></category>

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		<description><![CDATA[Click names for presentation PDF.
Moderator:

Mark Stalzer, CACR

Panelists:

Thomas Sterling, Louisiana State University
Allan Snavely, San Diego Supercomputer Center
Stephen Poole, Oak Ridge National Laboratory
William Camp, Intel Corporation

Abstract:
Over the next few years there are two boundary conditions that should constrain computer systems architecture: commodity components and applications performance. Yet, these two seem strangely disconnected. Perhaps we need some human [...]]]></description>
			<content:encoded><![CDATA[<p>Click names for presentation PDF.</p>
<p><strong>Moderator:</strong></p>
<ul>
<li><a href="http://www.cacr.caltech.edu/pubs_uploads/ArchPanelSC09/Stalzer.pdf"><strong>Mark Stalzer</strong></a>, CACR</li>
</ul>
<p><strong>Panelists:</strong></p>
<ul>
<li><a href="http://www.cacr.caltech.edu/pubs_uploads/ArchPanelSC09/Sterling.pdf">Thomas Sterling</a>, Louisiana State University</li>
<li><a href="http://www.cacr.caltech.edu/pubs_uploads/ArchPanelSC09/Snavely.pdf">Allan Snavely</a>, San Diego Supercomputer Center</li>
<li>Stephen Poole, Oak Ridge National Laboratory</li>
<li>William Camp, Intel Corporation</li>
</ul>
<p><strong>Abstract:</strong><br />
Over the next few years there are two boundary conditions that should constrain computer systems architecture: commodity components and applications performance. Yet, these two seem strangely disconnected. Perhaps we need some human optimization, as opposed to repeated use of Moore’s Law. Our panelists have been given a set of standard components that are on announced vendor roadmaps. They also each get to make one mystery component of no more complexity than a commercially available FPGA. The applications are HPL for linear algebra, Map-Reduce for databases, and a sequence matching algorithm for biology. The panelists have 10 minutes to disclose their systems architecture and mystery component, and estimate performance for the three applications at 1MW of power.</p>
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