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Macroservers: An Execution Model for DRAM Processor-In-Memory Arrays

Posted by cacrweb
March 6, 2000
Tags: architecture, parallel processing, PIM

Technical Report. California Institute of Technology. [CaltechCACR:CACR-2000-182]

Hans P. Zima and Thomas L. Sterling

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Macroservers: An Execution Model for DRAM Processor-In-Memory Arrays