FlashBlades: System Architecture and Applications

talk given at Architectures and Systems for Big Data (ASBD) 2012, Portland, Oregon.
Mark Stalzer

Presented is a speculative server blade architecture called a FlashBlade that combines 100x I/O performance in both latency and bandwidth with balanced computing. The blade consists of a standard multi-core CPU with attached DRAM. It uses a fast interconnect, such as Intel’s QuickPath, to communicate with a FPGA router called the X1. This router handles traffic to the “C1 complexes” and off-blade. Each C1 complex is a System on a Chip with Package on Package DRAM, connected to local flash memory. There are numerous complexes, giving tremendous I/O performance and computational balance. A large design space of parameters such as flash size, number of complexes, and link bandwidth between each C1 and the X1 is available for power and performance optimization. A single blade server constructed from these blades, just 12.25 inches high and drawing about 10 KW, could support a few hundred thousand basic web searches a second on 1 billion pages. It could also provide triple store performance 100x greater than achievable now for datasets of 6 TB and scales to petabyte datasets although at somewhat reduced performance; with numerous applications to defense, commerce, and science.

(PDF)