CACR Research Publications » Posts for tag 'PIM'

The “MIND” Scalable PIM Architecture

In: Advanced Research Workshop on High Performance Computing Technology and Applications, 31 May-3 June, 2004, Cetraro, Italy. [CaltechCACR:2005.102]

Thomas Sterling and Maciej Brodowicz

(PDF )

Macroservers: An Execution Model for DRAM Processor-In-Memory Arrays

Technical Report. California Institute of Technology. [CaltechCACR:CACR-2000-182]

Hans P. Zima and Thomas L. Sterling

(PDF)