Thomas L. Sterling

Faculty Associate, Center for Advanced Computing Research
California Institute of Technoglogy, MC 158-79
Pasadena, CA 91125
(626) 395-3901
tron@cacr.caltech.edu

Education

	Ph.D.E.E., Massachusetts Institute of Technology, Laboratory for Computer Science, June 1984
	E.E., Massachusetts Institute of Technology, Laboratory of Computer Science, February 1983
	S.M.E.E., Massachusetts Institute of Technology, Electrical Power Systems Engineering Laboratory, June 1981
	B.S.E.E., Old Dominion University, Electrical Engineering Department, Summa cum Laude, August 1974

Professional Experience

	June, 1996-present Principal Scientist, Jet Propulsion Laboratory
	March, 1999-present Faculty Associate, Center for Advanced Computing Research, California Institute of Technology
	June, 1996-March 1999 Visiting Associate, Center for Advanced Computing Research, California Institute of Technology
	January, 1995-June, 1996 Branch Head, USRA Center of Excellence in Space Data and Information Sciences, Goddard Space Flight Center
	July, 1994-June, 1996 Senior Scientist, USRA Center of Excellence in Space Data and Information Sciences, Goddard Space Flight Center
	July, 1994-present Adjunct Associate Professor, University of Maryland
	September, 1993-1994 Instructor, University of Maryland
	January, 1992-1994 Senior Scientist, USRA Center of Excellence in Space Data and Information Sciences, Goddard Space Flight Center
	May, 1988-1991 Research Staff Member, IDA Supercomputing Research Center
	June, 1983-1988 Senior Associate Principal Engineer (later Senior Principal Engineer), Harris Government Systems Sector
	September, 1977-1984 Various research and teaching assistantships and scholarships, Massachusetts Institute of Technology
	January, 1976-1977 VA Design Engineer, Sigma Consultants, Inc.
	May, 1970-1977 Aviation Electronics Technician First Class, United States Navy

Research Objectives and Directions

The achievement of high performance computing depends on high speed and capacity technologies, and the exploitation of parallel computing structures. Ultimately, practical computing capability is bounded by cost, whether measured in dollars, power consumption, or size. Delivered performance is a function of peak capacity and efficiency which for many parallel systems is itself determined by latency, overhead, contention, and starvation. My research objectives have been to devise 1) execution models that expose myriad forms of parallelism, 2) architecture structures that minimize these sources of performance degradation, 3) dynamic adaptive resource and task management mechanisms that further mitigate or hide the effects of such factors, and 4) software strategies that supervise application to system interfaces. To this end, I have engaged in research of a diversity of physical and abstract structures, often of my own devising. In addition, I am interested in the exploitation of highly replicated structures to provide dramatic reliability advances through dynamic graceful degradation.

Professional Activities

	Chair, Petaflops Architecture Workshop (PAWS), Oxnard, CA, April 22-25, 1996.
	Chair, IEEE Conference on Frontiers of Massively Parallel Processing, Annapolis, Maryland, 1996.
	Leader of heavily attended “How to Build a Beowulf” Tutorials at Supercomputing ’97 and ’99.
	President’s Information Technology Advisory committee (PITAC), Chair of High End computing panel on Petaflops/Petaflops computing.
	Chair, Petaflops-systems Operation Workshop, June 1998.
	Program chair, 2nd Conference on Enabling Technologies for Petaflops Computing, Santa Barbara, CA, February 15-19, 1999.
	Program Committee Member, IEEE Supercomputing conference, 1998-2002.
	Chair, Technical Program, IEEE International Conference on Cluster Computing, October 2001
	Program Committee Member for a Number of Other Conferences to Review Papers.
	Steering Committee Member, IEEE International Conference on Cluster Computing, 2001-2003.
	Contributor to DOD “Integrated High End Computing Initiative” (IHECI), Bowie, Maryland, 2002.
	Chair, Workshop on the Implementation of Multi PIM Systems, February 2002.
	High End Computing Study-Plenary Workshop Session, April 2002.
	Chair, Gordon Bell Awards Committee, IEEE Supercomputing Conference, November 2002.
	Program Vice-Chair for Multi-Agency High End Computing Revitalization Task Force (HECRTF) Workshop, Arlington, VA, June 17-18, 2003.

Honors and Awards

	Technology and Applications Program (TAP) Directorate "TECHNOLOGY SPOTLIGHT" 2000
	Gordon Bell Prize for Price Performance, 1997
	ICPP Best Presentation Award, 1988
	Hertz Foundation Fellowship, 1980
	ODU Electrical League Award, Scholarship Award, 1974

Books

	T. Sterling, P. Messina, P.H. Smith. Enabling Technologies for Petaflops Computing. MIT Press, Cambridge, MA, 1995.
	T. Sterling, J. Salmon, D.J. Becker, and D.F. Savarese. How to Build a Beowulf A Guide to the Implementation and application of PC Clusters. MIT Press, Cambridge, MA, 1999.

Books Edited

	P. Messina, T. Sterling, editors. System Software and Tools for High Performance Computing Environments. SIAM, Philadelphia, PA, 1993.
	T. Sterling, editor. Beowulf Cluster Computing with Linux. MIT Press, Cambridge, MA, 2001.
	T. Sterling, editor. Beowulf Cluster Computing with Windows. MIT Press, Cambridge, MA, 2001.
	W. Gropp, E. Lusk and T. Sterling. Beowulf Cluster Computing with Linux. MIT Press, Cambridge, MA 2003.

Journal Articles (Refereed)

	T. Sterling. Cluster Computing. Encyclopedia of Physical Science and Technology. 3rd edition, volume 3. Academic Press, 2002.
	T.M. Pinkston, A.F. Benner, M. Krause, I.M. Robinson, and T. Sterling. InfiniBand: The “De Facto” Future Standard for System and Local Area Networks or Just a scalable Replacement for PCI Buses? Cluster Computing, 6, 95-104, 2003.
	M. Baker, D.S. Katz, W. Gropp, and T. Sterling. Special Issue: Cluster 2001. Concurrency and Computation Practice & Experience, 15(7-8), 623-778, 2003.
	R. Biswas, J.C. Yan, W.F. Brooks, T.L. Sterling. High End Computing Technologies for Earch Science Applications: Trends, Challenges, and Innovations. Submitted to Computing in Science and Engineering.

Other Publications

	T. Sterling. Beowulf Breakthroughs: The genesis of Linux Clusters in high performance computing. Linux Magazine 6, 16-23, 2003.
	T. Sterling. Beowulf in Chrysalis. Cluster World, 1(1), 56, 2003.

Current Contracts and Grants

	DARPA, Dynamic Adaptive Architectures with Processor in Memory (PIM) Mechanisms for High Productivity Computing (Phase 2)
	Sandia National Laboratory, Processor in Memory Enhanced Mpp System Architecture for Acceleration of Data Intensive Applications.
	NASA Ames Research Center, Gilgamesh: Building a computer system from a large number of Processor-in-Memory (PIM) components.
	Argonne National Laboratory (DOE), Center for Programming Models for Scalable Parallel Computing.
	University of Delaware (NSF), A Framework for Developing Complex Applications on High-End Petaflop-Class Machines.

Biographical Sketch

Dr. Thomas Sterling holds a joint appointment as a Principal Scientist at the NASA Jet Propulsion Laboratory and as a Faculty Associate at Caltech's Center for Advanced Computing Research. Since receiving his Ph.D from MIT as a Hertz Fellow in 1984, Dr. Sterling has pursued a career of applied research in parallel computer architecture and high performance computing at Harris Corp, the IDA Supercomputing Research Center, and the NASA Goddard Space Flight Center and University of Maryland, joining Caltech and JPL in 1996. Thomas Sterling is widely recognized for his contributions to commodity cluster computing through the Beowulf Project which he started in 1994 and is the co-author of two books on clusters including "How to Build a Beowulf" and "Beowulf Cluster Computing". Dr. Sterling was the PI of the HTMT Project funded by a number of agencies to conduct the first multidisciplinary multi-institutional in-depth study of future Petaflops scale general purpose computers and is a co-author of a book on "Enabling Technologies for Petaflops Computing." Currently he is the PI of several projects that together are developing the MIND architecture, an advanced PIM computing component sponsored by NASA, Sandia National Laboratory, and DARPA.